FIELD OF THE INVENTION
The invention lies in the field of semiconductor technology. More specifically, the present invention relates to an integrated semiconductor memory configuration with a plurality of memory cell fields. A respective one of the memory cell fields can be activated at a given time as defined. The configuration further includes a voltage generator for delivering a supply potential to the memory cell fields, first electrical supply lines between the voltage generator and the plurality of memory cell fields, and second electrical supply lines between the plurality of memory cell fields.
To date, individual memory cell fields in integrated semiconductor memory configurations have each been connected with low resistance to a voltage generator via electrical supply lines in order to provide the individual memory cell fields with the supply voltage that is necessary in each case. Now, the individual memory cell fields in an integrated semiconductor memory configuration are activated successively as defined, so that, at a given instant, an accurately defined power quantity must be provided for a memory cell field which is currently activated.
The currently activated memory cell field thus forms an active region, while all the other memory cell fields represent inactive regions at the time that the activated memory cell field is activated.
Experiments have shown that it is sufficient to transfer a capacitance of approximately 70 pF in order to activate a memory cell field. A typical semiconductor memory configuration with a multiplicity of memory cell fields has a capacitance of approximately 2 nF available.